Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) cell is used for R-VDD architecture with improved stability lower consumption. developed to avoid unessential scaling. In this work, cells are implemented analyzed considering a technologically relevant 65 nm CMOS node. We analyze failure probability during read, write, mode, shows that proposed D2LP10T exhibits lowest rate compared other existing cells. Furthermore, design offers 1.66×, 4.0×, 1.15× higher stability, respectively, as 6T cell. Moreover, leakage power, write power-delay-product (PDP), PDP has been reduced by 89.96%, 80.52%, 59.80%, at 0.4 V voltage. functional improvement becomes even more apparent when quality factor (QF) evaluated, 458× than A significant of dissipation, i.e., 46.07% 74.55%, can also be observed conventional array respective operation